A layered approach for testing timing in the model-based implementation
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: 2014DOI: 10.1109/CICC.2014.6946102
Keyword(s): CMOS integrated circuits,adaptive equalisers,analogue-digital conversion,blind equalisers,clock and data recovery circuits,decision feedback equalisers,interpolation,radio receivers,CDR,CMOS,DFE,adaptive CTLE,analog phase interpolator,blind ADC,clock and data recovery circuits,continuous time linear equalizer,decision feedback equalizers,digital data interpolation,phase tracking ADC,Backplanes,CMOS integrated circuits,Decision feedback equalizers,Interpolation,Least square
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A layered approach for testing timing in the model-based implementation
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| date accessioned | 2020-03-12T19:40:33Z | |
| date available | 2020-03-12T19:40:33Z | |
| date issued | 2014 | |
| identifier other | 6800403.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/985801?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A layered approach for testing timing in the model-based implementation | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8101499 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | adaptive equalisers | |
| subject keywords | analogue-digital conversion | |
| subject keywords | blind equalisers | |
| subject keywords | clock and data recovery circuits | |
| subject keywords | decision feedback equalisers | |
| subject keywords | interpolation | |
| subject keywords | radio receivers | |
| subject keywords | CDR | |
| subject keywords | CMOS | |
| subject keywords | DFE | |
| subject keywords | adaptive CTLE | |
| subject keywords | analog phase interpolator | |
| subject keywords | blind ADC | |
| subject keywords | clock and data recovery circuits | |
| subject keywords | continuous time linear equalizer | |
| subject keywords | decision feedback equalizers | |
| subject keywords | digital data interpolation | |
| subject keywords | phase tracking ADC | |
| subject keywords | Backplanes | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Decision feedback equalizers | |
| subject keywords | Interpolation | |
| subject keywords | Least square | |
| identifier doi | 10.1109/CICC.2014.6946102 | |
| journal title | esign, Automation and Test in Europe Conference and Exhibition (DATE), 2014 | |
| filesize | 838981 | |
| citations | 0 | |
| contributor rawauthor | BaekGyu Kim , Hwang, H.I. , Taejoon Park , Son, S.H. , Insup Lee |