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Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control

contributor authorPanda, B. , Balachandran, S.
date accessioned2020-03-12T19:40:23Z
date available2020-03-12T19:40:23Z
date issued2014
identifier other6800293.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/985695?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleIntroducing Thread Criticality awareness in Prefetcher Aggressiveness Control
typeConference Paper
contenttypeMetadata Only
identifier padid8101376
subject keywordsCMOS digital integrated circuits
subject keywordsOFDM modulation
subject keywordsanalogue-digital conversion
subject keywordsquadrature amplitude modulation
subject keywordswireless LAN
subject keywordsOFDM
subject keywordsQAM16
subject keywordsWLAN
subject keywordsWiGig standard
subject keywordsdigital LP CMOS
subject keywordsfrequency 60 GHz
subject keywordsintegrated receiver front-end
subject keywordspower 39 mW
subject keywordssize 40 nm
subject keywordsskew-tolerant time-interleaved SAR ADC
subject keywordssuccessive approximation register analog-to-digital converter
subject keywordsvoltage 1.2 V
subject keywordsword length 8 bit
subject keywordsCMOS integrated circuits
subject keywordsCalibration
subject keywordsGain
subject keywordsOFDM
subject keywordsReceivers
subject keywordsSwitches
subject keywordsTiming
subject keywords802.11ad
subject keywordsADCs
subject keywordsSAR
subject keywordsTime-inte
identifier doi10.1109/CICC.2014.6945992
journal titleesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
filesize13296692
citations0


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