Effects of interlayers in threading dislocation reduction of step-graded InGaN heteroepitaxy
Publisher:
Year
: 2014DOI: 10.1109/RFIT.2014.6933266
Keyword(s): CMOS integrated circuits,high-speed integrated circuits,inductors,integrated circuit layout,oscillators,transistors,4-stage ring oscillator,CMOS,broadband high-speed circuits,differential pair layout styles,differential stacked spiral inductor,half-inter-digitated differential pair layout,inductance density,self-resonance frequency,size 65 nm,transistor layout designs,CMOS integrated circuits,Decision support systems,Inductance,Inductors,Layout,Metals,Transistors,Different
Collections
:
-
Statistics
Effects of interlayers in threading dislocation reduction of step-graded InGaN heteroepitaxy
Show full item record
| date accessioned | 2020-03-12T19:35:41Z | |
| date available | 2020-03-12T19:35:41Z | |
| date issued | 2014 | |
| identifier other | 6777885.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/983007?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Effects of interlayers in threading dislocation reduction of step-graded InGaN heteroepitaxy | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8098275 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | high-speed integrated circuits | |
| subject keywords | inductors | |
| subject keywords | integrated circuit layout | |
| subject keywords | oscillators | |
| subject keywords | transistors | |
| subject keywords | 4-stage ring oscillator | |
| subject keywords | CMOS | |
| subject keywords | broadband high-speed circuits | |
| subject keywords | differential pair layout styles | |
| subject keywords | differential stacked spiral inductor | |
| subject keywords | half-inter-digitated differential pair layout | |
| subject keywords | inductance density | |
| subject keywords | self-resonance frequency | |
| subject keywords | size 65 nm | |
| subject keywords | transistor layout designs | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Decision support systems | |
| subject keywords | Inductance | |
| subject keywords | Inductors | |
| subject keywords | Layout | |
| subject keywords | Metals | |
| subject keywords | Transistors | |
| subject keywords | Different | |
| identifier doi | 10.1109/RFIT.2014.6933266 | |
| journal title | lectrical Information and Communication Technology (EICT), 2013 International Conference on | |
| filesize | 323433 | |
| citations | 0 | |
| contributor rawauthor | Khatun, S. , Sanober, S.A. , Hossain, M.A. , Islam, M.R. |


