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A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation

date accessioned2020-03-12T19:30:46Z
date available2020-03-12T19:30:46Z
date issued2014
identifier other6742854.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/980194?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation
typeConference Paper
contenttypeMetadata Only
identifier padid8094464
subject keywordsmobile ad hoc networks
subject keywordspublic key cryptography
subject keywordsrouting protocols
subject keywordsAODV protocol
subject keywordsART
subject keywordsMANET
subject keywordsRSA algorithm
subject keywordsanonymous routing technique
subject keywordsdata protection
subject keywordsgood route anonymity protection
subject keywordsmobile ad hoc networks
subject keywordsmugger detection
subject keywordsone intense method
subject keywordsrandom node selection
subject keywordsrouting protocols
subject keywordssecure transmission
subject keywordsself organizing potential
subject keywordstransmission hierarchical zone partitioning
subject keywordsEncryption
subject keywordsMobile ad hoc networks
subject keywordsRouting
subject keywordsRouting protocols
subject keywordsAODV
subject keywordsAnonymity
subject keywordsRSA
subject keywordsSecurity
identifier doi10.1109/ICGCCEE.2014.6921382
journal titleesign Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific
filesize386722
citations0
contributor rawauthorWei Deng , Musa, A. , Siriburanon, T. , Miyahara, M. , Okada, K. , Matsuzawa, A.


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