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A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push–Pull Composite Power Transistor

contributor authorSau Siong Chong
contributor authorPak Kwong Chan
date accessioned2020-03-12T18:42:16Z
date available2020-03-12T18:42:16Z
date issued2014
identifier issn1063-8210
identifier other6719547.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/967476?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push–Pull Composite Power Transistor
typeJournal Paper
contenttypeMetadata Only
identifier padid8001470
subject keywordsCMOS integrated circuits
subject keywordscircuit stability
subject keywordscomposite materials
subject keywordspower MOSFET
subject keywordspower integrated circuits
subject keywordsOCL-LDO regulator
subject keywordsUMC CMOS technology
subject keywordscurrent 16.2 muA
subject keywordscurrent 50 mA
subject keywordsnondominant parasitic pole
subject keywordspush-pull composite power transistor
subject keywordssize 65 nm
subject keywordsslew rate limitation
subject keywordsstability
subject keywordstime 1.2 mus
subject keywordstransient-enhanced output-capacitorless low-dropout regulator
subject keywordsvoltage 0.75 V
subject keywordsvoltage 1 V
subject keywordsCapacitors
subject keywordsLogic gates
subject keywordsPower transistors
subject keywordsRegulators
subject keywordsStability analysis
subject keywordsTransistors
subject keywordsVoltage contro
identifier doi10.1109/TVLSI.2013.2290702
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue11
filesize2956768
citations1


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