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Single-Error-Correction and Double-Adjacent-Error-Correction Code for Simultaneous Testing of Data Bit and Check Bit Arrays in Memories

contributor authorSanguhn Cha
contributor authorHongil Yoon
date accessioned2020-03-12T18:40:01Z
date available2020-03-12T18:40:01Z
date issued2014
identifier issn1530-4388
identifier other6709746.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/966161?show=full
formatgeneral
languageEnglish
publisherIEEE
titleSingle-Error-Correction and Double-Adjacent-Error-Correction Code for Simultaneous Testing of Data Bit and Check Bit Arrays in Memories
typeJournal Paper
contenttypeMetadata Only
identifier padid7999934
subject keywordserror correction codes
subject keywordsmemory architecture
subject keywordsradiation hardening (electronics)
subject keywordstesting
subject keywordsSEC DAEC code
subject keywordscheck bit arrays
subject keywordsdata bit arrays
subject keywordsdouble adjacent error correction code
subject keywordsinterword coupling faults
subject keywordsintraword coupling faults
subject keywordsmemory array tests
subject keywordsmemory fault models
subject keywordssimultaneous testing
subject keywordssingle cell faults
subject keywordssingle error correction code
subject keywordsArrays
subject keywordsError correction codes
subject keywordsGenerators
subject keywordsHardware
subject keywordsMaterials reliability
subject keywordsTesting
subject keywordsVectors
subject keywordsError correction code
subject keywordsfault model
subject keywordsmemory test
subject keywordsword-orient
identifier doi10.1109/TDMR.2014.2299595
journal titleDevice and Materials Reliability, IEEE Transactions on
journal volume14
journal issue1
filesize260599
citations0


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