Two-stage logarithmic converter with reduced memory requirements
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Year
: 2014DOI: 10.1049/iet-cdt.2012.0134
Keyword(s): convertors,digital arithmetic,field programmable gate arrays,piecewise linear techniques,piecewise polynomial techniques,read-only storage,reconfigurable architectures,ROM,Spartan6 XC6SLX16 device,Xilinx Spartan3 FPGA,Xilinx Spartan6 FPGA,arithmetic components,binary logarithm,block RAM,fractional precision,frequency 127.8 MHz,frequency 160 MHz,frequency 42.3 MHz,frequency 71.4 MHz,logic slices,multipliers,nonuniform piecewise linear techniques,nonuniform piecewise polynomi
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Two-stage logarithmic converter with reduced memory requirements
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| contributor author | Chaudhary, Mandeep | |
| contributor author | Lee, P. | |
| date accessioned | 2020-03-12T18:38:08Z | |
| date available | 2020-03-12T18:38:08Z | |
| date issued | 2014 | |
| identifier issn | 1751-8601 | |
| identifier other | 6695818.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/965090 | |
| format | general | |
| language | English | |
| publisher | IET | |
| title | Two-stage logarithmic converter with reduced memory requirements | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7998696 | |
| subject keywords | convertors | |
| subject keywords | digital arithmetic | |
| subject keywords | field programmable gate arrays | |
| subject keywords | piecewise linear techniques | |
| subject keywords | piecewise polynomial techniques | |
| subject keywords | read-only storage | |
| subject keywords | reconfigurable architectures | |
| subject keywords | ROM | |
| subject keywords | Spartan6 XC6SLX16 device | |
| subject keywords | Xilinx Spartan3 FPGA | |
| subject keywords | Xilinx Spartan6 FPGA | |
| subject keywords | arithmetic components | |
| subject keywords | binary logarithm | |
| subject keywords | block RAM | |
| subject keywords | fractional precision | |
| subject keywords | frequency 127.8 MHz | |
| subject keywords | frequency 160 MHz | |
| subject keywords | frequency 42.3 MHz | |
| subject keywords | frequency 71.4 MHz | |
| subject keywords | logic slices | |
| subject keywords | multipliers | |
| subject keywords | nonuniform piecewise linear techniques | |
| subject keywords | nonuniform piecewise polynomi | |
| identifier doi | 10.1049/iet-cdt.2012.0134 | |
| journal title | Computers & Digital Techniques, IET | |
| journal volume | 8 | |
| journal issue | 1 | |
| filesize | 351100 | |
| citations | 0 |