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A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW

contributor authorKauffman, John G.
contributor authorWitte, Pascal
contributor authorLehmann, Matthias
contributor authorBecker, Jurgen
contributor authorManoli, Yiannos
contributor authorOrtmanns, Maurits
date accessioned2020-03-12T18:33:58Z
date available2020-03-12T18:33:58Z
date issued2014
identifier issn0018-9200
identifier other6674069.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/962714?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW
typeJournal Paper
contenttypeMetadata Only
identifier padid7995809
subject keywordsCMOS integrated circuits
subject keywordsamplifiers
subject keywordsdelta-sigma modulation
subject keywordslinearisation techniques
subject keywordstable lookup
subject keywordsCMOS process
subject keywordsamplifier
subject keywordsauxiliary DAC linearization
subject keywordsbandwidth 25 MHz
subject keywordsbandwidth 500 MHz
subject keywordsbinary test signal
subject keywordscontinuous time &
subject keywords#x0394
subject keywords&
subject keywords#x03A3
subject keywordsmodulator
subject keywordscross correlation
subject keywordsdigitally estimated linearization
subject keywordsdynamic element matching
subject keywordsfinite gain bandwidth compensation
subject keywordslookup-table
subject keywordsloop delay
subject keywordsloop filter stability
subject keywordsmultibit &
subject keywords#x0394
subject keywords&
subject keywords#x03A3
subject keywordsmodulators
subject keywordsmultibit operation
subject keywordsover
identifier doi10.1109/JSSC.2013.2289887
journal titleSolid-State Circuits, IEEE Journal of
journal volume49
journal issue2
filesize2793972
citations0


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