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A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

contributor authorYankang Du
contributor authorShuming Chen
contributor authorBiwei Liu
date accessioned2020-03-12T18:33:21Z
date available2020-03-12T18:33:21Z
date issued2014
identifier issn1530-4388
identifier other6670093.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/962390?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits
typeJournal Paper
contenttypeMetadata Only
identifier padid7995385
subject keywordscombinational circuits
subject keywordsintegrated circuit layout
subject keywordsradiation hardening (electronics)
subject keywordsradiation quenching
subject keywordscombinational circuits
subject keywordsconstrained layout placement
subject keywordspulse quenching effect
subject keywordsquenching cells
subject keywordssoft error vulnerability
subject keywordsCombinational circuits
subject keywordsIons
subject keywordsLayout
subject keywordsLogic gates
subject keywordsMOSFET
subject keywordsStandards
subject keywordsVectors
subject keywordsConstrained layout
subject keywordsmulti-node charge collection
subject keywordspulse quenching effect
subject keywordsquenching cells
identifier doi10.1109/TDMR.2013.2291409
journal titleDevice and Materials Reliability, IEEE Transactions on
journal volume14
journal issue1
filesize1606292
citations0


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