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Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

contributor authorByoung-Joo Yoo
contributor authorWoo-Rham Bae
contributor authorJiho Han
contributor authorJaeha Kim
contributor authorDeog-Kyoon Jeong
date accessioned2020-03-12T18:24:38Z
date available2020-03-12T18:24:38Z
date issued2014
identifier issn1063-8210
identifier other6549110.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/957554?show=full
formatgeneral
languageEnglish
publisherIEEE
titleLinearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit
typeJournal Paper
contenttypeMetadata Only
identifier padid7989839
subject keywordsCMOS integrated circuits
subject keywordsclock and data recovery circuits
subject keywordslinearisation techniques
subject keywordsphase detectors
subject keywordssynchronisation
subject keywordstiming circuits
subject keywordsCMOS technology
subject keywordsbinary phase detectors
subject keywordscollaborative timing recovery circuit
subject keywordsfinite latency difference
subject keywordslinear information
subject keywordslinear loop dynamics
subject keywordslinearization technique
subject keywordsmultichannel clock and data recovery circuit
subject keywordsphase errors
subject keywordssize 45 nm
subject keywordsBinary phase detector (PD)
subject keywordsclock and data recovery circuit (CDR)
subject keywordsdigital control
subject keywordslinearization techniques
subject keywordsserial
identifier doi10.1109/TVLSI.2013.2269616
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue6
filesize1624727
citations0


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