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Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test

contributor authorMingjing Chen
contributor authorOrailoglu, A.
date accessioned2020-03-12T18:23:23Z
date available2020-03-12T18:23:23Z
date issued2014
identifier issn1063-8210
identifier other6515389.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/956836?show=full
formatgeneral
languageEnglish
publisherIEEE
titleExamining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test
typeJournal Paper
contenttypeMetadata Only
identifier padid7988970
subject keywordsautomatic test pattern generation
subject keywordsintegrated circuit noise
subject keywordsintegrated circuit reliability
subject keywordsintegrated circuit testing
subject keywordsnanoelectronics
subject keywordspower supply circuits
subject keywordsSPICE-accurate estimation
subject keywordsat-speed functional cycles
subject keywordsat-speed testing techniques
subject keywordscircuit layout
subject keywordscircuit robustness
subject keywordscircuit timing
subject keywordscompound noise profile
subject keywordsdelay testing schemes
subject keywordslinear superposition
subject keywordslow-frequency noise
subject keywordsmarginal timing failures
subject keywordsmiddle-frequency noise
subject keywordsmultifunctional-cycle delay test
subject keywordsmultifunctional-cycle test sc
identifier doi10.1109/TVLSI.2013.2256810
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue4
filesize2132797
citations0


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