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Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains

contributor authorChabloz, Jean-Michel
contributor authorHemani, Ahmed
date accessioned2020-03-12T18:22:56Z
date available2020-03-12T18:22:56Z
date issued2014
identifier issn1063-8210
identifier other6507330.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/956586?show=full
formatgeneral
languageEnglish
publisherIEEE
titleLow-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
typeJournal Paper
contenttypeMetadata Only
identifier padid7988658
subject keywordsclocks
subject keywordslogic design
subject keywordssynchronisation
subject keywordsasynchronous first-input first-output GALS interface
subject keywordsfrequency submultiples
subject keywordsglobally asynchronous design subset
subject keywordsglobally ratiochronous design
subject keywordslocally synchronous design subset
subject keywordslow latency maximal throughput communication interface
subject keywordsrationally related clock domains
subject keywordsrationally related clock frequency
subject keywordssource synchronous adaptive interface
subject keywordsApplication specific integrated circuits
subject keywordsasynchronous circuits
subject keywordscircuits
subject keywordscircuits and systems
subject keywordssystem-on-a-chip
identifier doi10.1109/TVLSI.2013.2252030
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue3
filesize762743
citations0


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