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Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

contributor authorBhoj, Ajay N.
contributor authorJha, Niraj K.
date accessioned2020-03-12T18:22:47Z
date available2020-03-12T18:22:47Z
date issued2014
identifier issn1063-8210
identifier other6502262.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/956499?show=full
formatgeneral
languageEnglish
publisherIEEE
titleParasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs
typeJournal Paper
contenttypeMetadata Only
identifier padid7988542
subject keywordsMOSFET
subject keywordsSRAM chips
subject keywordslogic design
subject keywordstechnology CAD (electronics)
subject keywordsasymmetric gate workfunction FinFET SRAM
subject keywordsfin pitches
subject keywordsmixed mode 2D TCAD technology circuit codesign methodology
subject keywordsmixed mode transient device simulations
subject keywordsmultigate FET technology
subject keywordsparasitic capacitances
subject keywordsparasitics aware design
subject keywordsplanar CMOS technology
subject keywordssilicon on insulator process
subject keywordssize 22 nm
subject keywordsstructure synthesis algorithms
subject keywordstransport analysis
subject keywordsFinFET
subject keywordsSRAM
subject keywordsmultigate FET
subject keywordsparasitics
subject keywordsstructure synthesis
identifier doi10.1109/TVLSI.2013.2252031
journal titleVery Large Scale Integration (VLSI) Systems, IEEE Transactions on
journal volume22
journal issue3
filesize2365974
citations0


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