Ultra-High Throughput Low-Power Packet Classification
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: 2014DOI: 10.1109/TVLSI.2013.2241798
Keyword(s): field programmable gate arrays,integrated memory circuits,parallel processing,power consumption,FPGA,HyperCuts packet classification algorithm,Stratix III field-programmable gate array,floating point division,hardware accelerator,headers,networking equipment,on-chip memory,power 9.03 W,power consumption,pre-cutting process,rulesets,ultra-high throughput low-power packet classification,Compaction,Decision trees,Electronics packaging,Hardware,IP networks,Memory management,Th
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Ultra-High Throughput Low-Power Packet Classification
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| contributor author | Kennedy, A. | |
| contributor author | Xiaojun Wang | |
| date accessioned | 2020-03-12T18:21:38Z | |
| date available | 2020-03-12T18:21:38Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6459611.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/955860 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Ultra-High Throughput Low-Power Packet Classification | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7987661 | |
| subject keywords | field programmable gate arrays | |
| subject keywords | integrated memory circuits | |
| subject keywords | parallel processing | |
| subject keywords | power consumption | |
| subject keywords | FPGA | |
| subject keywords | HyperCuts packet classification algorithm | |
| subject keywords | Stratix III field-programmable gate array | |
| subject keywords | floating point division | |
| subject keywords | hardware accelerator | |
| subject keywords | headers | |
| subject keywords | networking equipment | |
| subject keywords | on-chip memory | |
| subject keywords | power 9.03 W | |
| subject keywords | power consumption | |
| subject keywords | pre-cutting process | |
| subject keywords | rulesets | |
| subject keywords | ultra-high throughput low-power packet classification | |
| subject keywords | Compaction | |
| subject keywords | Decision trees | |
| subject keywords | Electronics packaging | |
| subject keywords | Hardware | |
| subject keywords | IP networks | |
| subject keywords | Memory management | |
| subject keywords | Th | |
| identifier doi | 10.1109/TVLSI.2013.2241798 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 2 | |
| filesize | 1087970 | |
| citations | 0 |