The Well-Connected Processor Array
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: 2014DOI: 10.1109/TC.2012.280
Keyword(s): fast Fourier transforms,graph theory,multiprocessor interconnection networks,network routing,reconfigurable architectures,PE,RMESH,WECPAR connectivity,broadcasting,complex switching configurations,graph embeddings,logarithmic time,n-point FFT,point-to-point lines,processing element,reconfigurable buses,reconfigurable mesh,reconfigurable processor arrays,self-simulation,switch area,transportation-type routing method,well-connected processor array,Binary trees,Computer graph
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The Well-Connected Processor Array
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| contributor author | Gordon, D. | |
| date accessioned | 2020-03-12T18:20:55Z | |
| date available | 2020-03-12T18:20:55Z | |
| date issued | 2014 | |
| identifier issn | 0018-9340 | |
| identifier other | 6361379.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/955525 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | The Well-Connected Processor Array | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7987194 | |
| subject keywords | fast Fourier transforms | |
| subject keywords | graph theory | |
| subject keywords | multiprocessor interconnection networks | |
| subject keywords | network routing | |
| subject keywords | reconfigurable architectures | |
| subject keywords | PE | |
| subject keywords | RMESH | |
| subject keywords | WECPAR connectivity | |
| subject keywords | broadcasting | |
| subject keywords | complex switching configurations | |
| subject keywords | graph embeddings | |
| subject keywords | logarithmic time | |
| subject keywords | n-point FFT | |
| subject keywords | point-to-point lines | |
| subject keywords | processing element | |
| subject keywords | reconfigurable buses | |
| subject keywords | reconfigurable mesh | |
| subject keywords | reconfigurable processor arrays | |
| subject keywords | self-simulation | |
| subject keywords | switch area | |
| subject keywords | transportation-type routing method | |
| subject keywords | well-connected processor array | |
| subject keywords | Binary trees | |
| subject keywords | Computer graph | |
| identifier doi | 10.1109/TC.2012.280 | |
| journal title | Computers, IEEE Transactions on | |
| journal volume | 63 | |
| journal issue | 5 | |
| filesize | 1613873 | |
| citations | 0 |