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A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations

contributor authorسیده ساره مجیدی ایوریen
contributor authorمحمد میمندی نژادen
contributor authorSeyedeh Sareh Majidi Ivarifa
contributor authorMohammad Maymandi Nejadfa
date accessioned2020-06-06T14:10:37Z
date available2020-06-06T14:10:37Z
date copyright5/14/2013
date issued2013
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/3385641?show=full
description abstractAbstract— Designing logic circuits in the subthreshold regime is

one of the most effective ways to reduce the power consumption

of digital circuits. In the subthreshold region, the current is an

exponential function of the threshold voltage and the behavior of

transistors is more susceptible to process variations. In this

paper, we present a new design technique that helps reduce the

impact of process variations on the circuit. The proposed

technique is implemented on the staticC2MOS flip-flop and the

flip flop is used in a shift register. The circuit is simulated in the

90nm CMOS technology using a 0.2V supply voltage. Simulation

results show that the robustness of the circuit is improved while

the power consumption and the area are kept at minimum.		en
languageEnglish
titleA New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variationsen
typeConference Paper
contenttypeExternal Fulltext
subject keywordsDigital circuiten
subject keywordsCMOSen
subject keywordsSub-thresholden
subject keywordsrobustnessen
subject keywordslow poweren
identifier linkhttps://profdoc.um.ac.ir/paper-abstract-1035639.html
conference titleبیست و یکمین کنفرانس مهندسی برق ایرانfa
conference locationمشهدfa
identifier articleid1035639


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