Segmented Architecture for Successive Approximation Analog-to-Digital Converters

Abstract

In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC) in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce the power consumption and improve the static linearity performance. In order to be able to choose the optimum value of the segmentation degree (i.e. the number of unary bits), the power consumption and the static linearity behavior of the segmented architecture as functions of the segmentation degree are analyzed. Circuit-level simulation results are presented to show the accuracy of the proposed equations. It is shown that for moderate and high resolution ADCs, a segmentation degree of 4 or 5 bits is the optimum choice from the power-consumption viewpoint. Simulation results of a 1-V 10-bit 100-kS/s SA-ADC shows that the power consumption of the entire capacitive DAC and the digital circuit of the segmented implementation with a segmentation degree of 4 is 30% less than the conventional design while the standard deviation of the differential-non-linearity (DNL) is reduced by a factor of 2√2.