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contributor authorمحمد طاهرزاده ثانیen
contributor authorAnas A. Hamouien
contributor authorMohammad Taherzadeh-Sanifa
date accessioned2020-06-06T13:11:39Z
date available2020-06-06T13:11:39Z
date issued2006
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/3345350?show=full
description abstractA digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the feedback capacitor with the sampling capacitor(s) in the multiplying digital-to-analog converter (MDAC) of each pipeline stage in the pipelined ADC. The capacitor-mismatch errors in all pipeline stages are then concurrently measured and corrected in the digital domain. The proposed technique can be utilized in both single-bit and multibit MDACs. Owing to its simple iterative algorithm for capacitor-mismatch error calibration, its implementation requires minimal additional digital hardware. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-plus-distortion ratio is improved from 10 to 12.5bits and the spurious-free dynamic range is increased from 65 to 95 dB, in a 13-bit pipelined ADC with sigma=0.25% capacitor mismatchesen
languageEnglish
titleDigital Background Calibration of Capacitor Mismatch Errors in Pipelined ADCsen
typeJournal Paper
contenttypeExternal Fulltext
subject keywordsAnalog-to-digital conversionen
subject keywordscapacitor mismatchen
subject keywordsdigital background calibrationen
subject keywordspipelined analog-to-digital converter (ADC)en
journal titleIEEE Transactions on Circuits and Systems Part II: Express Briefsfa
pages966-970
journal volume53
journal issue9
identifier linkhttps://profdoc.um.ac.ir/paper-abstract-1032872.html
identifier articleid1032872


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