Design of Logic Gates and Flip-Flops in High-performance FinFET Technology
| contributor author | Bhoj, Ajay N. | |
| contributor author | Jha, Niraj K. | |
| date accessioned | 2020-03-10T15:40:02Z | |
| date available | 2020-03-10T15:40:02Z | |
| date issued | 2013 | |
| identifier other | MjnrSVnbfzqZL4qC43IyklPyI4fMWD03m0QoOfb9N9kyZYmD7_.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/206689?show=full | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Design of Logic Gates and Flip-Flops in High-performance FinFET Technology | |
| type | Journal Paper | |
| contenttype | Fulltext | |
| contenttype | Fulltext | |
| identifier padid | 1307031 | |
| identifier doi | 10.1109/TVLSI.2012.2227850 | |
| journal title | IEEE Transactions on Very Large Scale Integration Systems | |
| coverage | Academic | |
| pages | 1-1 | |
| filesize | 1542182 | |
| citations | 1 |