A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS

contributor author	Xiaoyang Wang
contributor author	Qiang Li
date accessioned	2020-03-14T11:25:34Z
date available	2020-03-14T11:25:34Z
date issued	2014
identifier other	IXOIq_lAETIIR_DkJGzbkhUkfTi54Czy5FKy3GhCUYjoaAYgZ1.pdf
identifier uri	https://libsearch.um.ac.ir:443/fum/handle/fum/1631441?show=full
format	general
language	English
title	A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS
type	Journal Paper
contenttype	Fulltext
contenttype	Fulltext
identifier padid	11761200
identifier doi	10.1109/ISCAS.2014.6865127
journal title	2014 IEEE International Symposium on Circuits and Systems (ISCAS)
coverage	Academic
filesize	622208
citations	1