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Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

contributor authorNayak, Kaushik
contributor authorAgarwal, Sankalp
contributor authorBajaj, Mohit
contributor authorOldiges, Philip J.
contributor authorMurali, Kota V. R. M.
contributor authorRao, Valipe Ramgopal
date accessioned2020-03-13T00:22:03Z
date available2020-03-13T00:22:03Z
date issued2014
identifier issn0018-9383
identifier other6895292.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1144063?show=full
formatgeneral
languageEnglish
publisherIEEE
titleMetal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs
typeJournal Paper
contenttypeMetadata Only
identifier padid8326712
subject keywordsMOSFET
subject keywordselemental semiconductors
subject keywordsnanowires
subject keywordssilicon
subject keywordsstatistical analysis
subject keywordstitanium compounds
subject keywordsGAA n-NWFET
subject keywordsSi
subject keywordsTiN
subject keywordscoupled 3D statistical device simulations
subject keywordsfigure of merit
subject keywordsgate-all-around nanowire n-MOSFET
subject keywordslinear mode
subject keywordsmetal-gate crystal grain size
subject keywordsmetal-gate granularity-induced threshold voltage variability
subject keywordsquantum corrected room temperature drift-diffusion transport
subject keywordssaturation mode
subject keywordstemperature 293 K to 298 K
subject keywordsFinFETs
subject keywordsGrain size
subject keywordsLogic gates
subject keywordsNanoscale devices
subject keywordsSilicon
subject keywordsGate-all-aro
identifier doi10.1109/TED.2014.2351401
journal titleElectron Devices, IEEE Transactions on
journal volume61
journal issue11
filesize1314273
citations1


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