Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices
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سال
: 2014شناسه الکترونیک: 10.1109/TCPMT.2014.2339272
کلیدواژه(گان): cost reduction,integrated circuit noise,integrated circuit packaging,IC chip,IC products,cost minimization,die design methodology,inductive noise,innovative scaling method,integrated circuit packages,optimum package solutions,power delivery solutions,Capacitance,Clocks,Inductance,Noise,Power supplies,Resistance,Silicon,(L) , (C) , and (R) of packages,Die decoupling capacitance,L, C, and R of packages,die decoupling resistance,organic land grid array core/coreless packages
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آمار بازدید
Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices
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| contributor author | Bhattacharyya, Bidyut K. | |
| contributor author | Laskar, Nivedita | |
| contributor author | Debnath, Shoubhik | |
| contributor author | Baral, Debasis | |
| date accessioned | 2020-03-13T00:17:42Z | |
| date available | 2020-03-13T00:17:42Z | |
| date issued | 2014 | |
| identifier issn | 2156-3950 | |
| identifier other | 6874514.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1141432 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8323869 | |
| subject keywords | cost reduction | |
| subject keywords | integrated circuit noise | |
| subject keywords | integrated circuit packaging | |
| subject keywords | IC chip | |
| subject keywords | IC products | |
| subject keywords | cost minimization | |
| subject keywords | die design methodology | |
| subject keywords | inductive noise | |
| subject keywords | innovative scaling method | |
| subject keywords | integrated circuit packages | |
| subject keywords | optimum package solutions | |
| subject keywords | power delivery solutions | |
| subject keywords | Capacitance | |
| subject keywords | Clocks | |
| subject keywords | Inductance | |
| subject keywords | Noise | |
| subject keywords | Power supplies | |
| subject keywords | Resistance | |
| subject keywords | Silicon | |
| subject keywords | (L) , (C) , and (R) of packages | |
| subject keywords | Die decoupling capacitance | |
| subject keywords | L, C, and R of packages | |
| subject keywords | die decoupling resistance | |
| subject keywords | organic land grid array core/coreless packages | |
| identifier doi | 10.1109/TCPMT.2014.2339272 | |
| journal title | Components, Packaging and Manufacturing Technology, IEEE Transactions on | |
| journal volume | 4 | |
| journal issue | 9 | |
| filesize | 1815189 | |
| citations | 0 |