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High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards

contributor authorShrestha, Ranjay
contributor authorPaily, Roy P.
date accessioned2020-03-13T00:12:02Z
date available2020-03-13T00:12:02Z
date issued2014
identifier issn1549-8328
identifier other6847747.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1137978?show=full
formatgeneral
languageEnglish
publisherIEEE
titleHigh-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards
typeJournal Paper
contenttypeMetadata Only
identifier padid8319970
subject keywords3G mobile communication
subject keywordsCMOS integrated circuits
subject keywordsLong Term Evolution
subject keywordsVLSI
subject keywordsintegrated circuit design
subject keywordsmaximum likelihood decoding
subject keywordstelecommunication standards
subject keywordsturbo codes
subject keywords3GPP-LTE standard
subject keywords90 nm CMOS technology
subject keywordsACSU
subject keywordsLBCJR algorithm
subject keywordsLTE wireless communication standards
subject keywordsLTE-Advanced standard
subject keywordsVLSI design aspect
subject keywordsadd-compare-select-unit
subject keywordsbackward state metric computation
subject keywordscritical path delay reduction
subject keywordshigh-speed maximum a posteriori probability decoders
subject keywordshigh-throughput turbo decoder
subject keywordsit
identifier doi10.1109/TCSI.2014.2332266
journal titleCircuits and Systems I: Regular Papers, IEEE Transactions on
journal volume61
journal issue9
filesize3155839
citations0


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