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Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning

contributor authorPradhan, Manjari
contributor authorDas, Debesh K.
contributor authorGiri, Chandan
contributor authorRahaman, Hafizur
date accessioned2020-03-12T22:52:27Z
date available2020-03-12T22:52:27Z
date issued2014
identifier other7027044.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1097533?show=full
formatgeneral
languageEnglish
publisherIEEE
titleOptimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning
typeConference Paper
contenttypeMetadata Only
identifier padid8238387
subject keywordsAlgebra
subject keywordsn Bifurcation
subject keywordsn Educational institutions
subject keywordsn Mathematical model
subject keywordsn Nonlinear circuits
subject keywordsn Oscillators
subject keywordsn Hyperbolic Numbers
subject keywordsn Non-Smooth Time Transformation
subject keywordsn Nonlinear Circuits
subject keywordsn Periodic Oscillations
identifier doi10.1109/MWSCAS.2014.6908443
journal titleesign & Test Symposium (EWDTS), 2014 East-West
filesize529668
citations0


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