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Educating hardware design — From boolean equations to massively parallel computing systems

contributor authorKnodel, Oliver
contributor authorZabel, Martin
contributor authorLehmann, Patrick
contributor authorSpallek, Rainer G.
date accessioned2020-03-12T22:18:11Z
date available2020-03-12T22:18:11Z
date issued2014
identifier other7002216.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1078314?show=full
formatgeneral
languageEnglish
publisherIEEE
titleEducating hardware design — From boolean equations to massively parallel computing systems
typeConference Paper
contenttypeMetadata Only
identifier padid8214605
subject keywordsMOSFET
subject keywordsn SRAM chips
subject keywordsn circuit stability
subject keywordsn compensation
subject keywordsn integrated circuit design
subject keywordsn integrated circuit reliability
subject keywordsn negative bias temperature instability
subject keywordsn semiconductor device reliability
subject keywordsn sensors
subject keywordsn HSPICE simulation
subject keywordsn NBTI
subject keywordsn PTM IG-FinFET technology
subject keywordsn RNM
subject keywordsn SNM
subject keywordsn SRAM array Design
subject keywordsn adaptable trip-point sensing technique
subject keywordsn compensation technique
subject keywordsn independent gate FinFET
subject keywordsn negative bias temperature instability
subject keywordsn reliability
subject keywordsn self
identifier doi10.1109/NANOARCH.2014.6880481
journal titlerogrammable Logic (SPL), 2014 IX Southern Conference on
filesize150157
citations0


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