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Low power look-up table topologies for FPGAs

contributor authorSubbareddy, Thadigotla Venkata
contributor authorReddy, Bommepalli Madhava
contributor authorUpadhyay, Har Narayan
contributor authorElamaran, V
date accessioned2020-03-12T22:06:00Z
date available2020-03-12T22:06:00Z
date issued2014
identifier other6992936.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1071376?show=full
formatgeneral
languageEnglish
publisherIEEE
titleLow power look-up table topologies for FPGAs
typeConference Paper
contenttypeMetadata Only
identifier padid8207448
subject keywordscalibration
subject keywordsn network analysers
subject keywordsn 12-term error model
subject keywordsn TOSM
subject keywordsn VNA
subject keywordsn full 2-port method
subject keywordsn incomplete 2-port vector network analyzer calibration method
subject keywordsn Calibration
subject keywordsn Equations
subject keywordsn Mathematical model
subject keywordsn Measurement uncertainty
subject keywordsn Reflection
subject keywordsn Scattering parameters
subject keywordsn Uncertainty
identifier doi10.1109/ARGENCON.2014.6868593
journal titleontrol, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International
filesize544524
citations0


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