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Optimizing Krylov Subspace Solvers on Graphics Processing Units

contributor authorAnzt, Hartwig
contributor authorSawyer, William
contributor authorTomov, Stanimire
contributor authorLuszczek, Piotr
contributor authorYamazaki, Ichitaro
contributor authorDongarra, Jack
date accessioned2020-03-12T21:59:21Z
date available2020-03-12T21:59:21Z
date issued2014
identifier other6969483.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1067540?show=full
formatgeneral
languageEnglish
publisherIEEE
titleOptimizing Krylov Subspace Solvers on Graphics Processing Units
typeConference Paper
contenttypeMetadata Only
identifier padid8202258
subject keywordsfield programmable gate arrays
subject keywordsn NetFPGA card
subject keywordsn behavioral functionality
subject keywordsn clock resolution
subject keywordsn data link layer
subject keywordsn forwarding packets
subject keywordsn high resolution hardware
subject keywordsn higher layer pass
subject keywordsn network parameters
subject keywordsn packet arrival
subject keywordsn packet capture
subject keywordsn packet capture cards
subject keywordsn protocol functions
subject keywordsn Clocks
subject keywordsn Hardware
subject keywordsn IP networks
subject keywordsn Monitoring
subject keywordsn Payloads
subject keywordsn Radiation detectors
subject keywordsn Software
subject keywordsn hardware speed
subject keywordsn high resolution
subject keywordsn high speed
subject keywordsn packet captur
identifier doi10.1109/WOCC.2014.6839926
journal titlearallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International
filesize423183
citations0


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