contributor author | Maneesha, K. | |
contributor author | Chris Prema, S. | |
date accessioned | 2020-03-12T21:36:56Z | |
date available | 2020-03-12T21:36:56Z | |
date issued | 2014 | |
identifier other | 6949875.pdf | |
identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1054609?show=full | |
format | general | |
language | English | |
publisher | IEEE | |
title | A Channel Combiner approach for the design of Near Perfect Reconstruction non uniform Filter Banks | |
type | Conference Paper | |
contenttype | Metadata Only | |
identifier padid | 8185236 | |
subject keywords | cache storage | |
subject keywords | n integrated circuit reliability | |
subject keywords | n PV effect | |
subject keywords | n PV-induced timing-errors | |
subject keywords | n asymmetric pipelining | |
subject keywords | n dynamic locality | |
subject keywords | n high-error rate L1 cache | |
subject keywords | n implementation cost | |
subject keywords | n latency overhead | |
subject keywords | n logic path depth | |
subject keywords | n low-error rate L1 cache | |
subject keywords | n medium-error rate L1 cache | |
subject keywords | n modern processor | |
subject keywords | n performance overhead reduction | |
subject keywords | n power overhead | |
subject keywords | n process-variation effect | |
subject keywords | n reliability concern | |
subject keywords | n robust L1 cache design | |
subject keywords | n semiconductor industry | |
subject keywords | n st | |
identifier doi | 10.1109/ISQED.2014.6783300 | |
journal title | ommunications and Signal Processing (ICCSP), 2014 International Conference on | |
filesize | 1206568 | |
citations | 0 | |