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contributor authorManeesha, K.
contributor authorChris Prema, S.
date accessioned2020-03-12T21:36:56Z
date available2020-03-12T21:36:56Z
date issued2014
identifier other6949875.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1054609?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Channel Combiner approach for the design of Near Perfect Reconstruction non uniform Filter Banks
typeConference Paper
contenttypeMetadata Only
identifier padid8185236
subject keywordscache storage
subject keywordsn integrated circuit reliability
subject keywordsn PV effect
subject keywordsn PV-induced timing-errors
subject keywordsn asymmetric pipelining
subject keywordsn dynamic locality
subject keywordsn high-error rate L1 cache
subject keywordsn implementation cost
subject keywordsn latency overhead
subject keywordsn logic path depth
subject keywordsn low-error rate L1 cache
subject keywordsn medium-error rate L1 cache
subject keywordsn modern processor
subject keywordsn performance overhead reduction
subject keywordsn power overhead
subject keywordsn process-variation effect
subject keywordsn reliability concern
subject keywordsn robust L1 cache design
subject keywordsn semiconductor industry
subject keywordsn st
identifier doi10.1109/ISQED.2014.6783300
journal titleommunications and Signal Processing (ICCSP), 2014 International Conference on
filesize1206568
citations0


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