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Advanced modeling and simulation of state-of-the-art high-speed I/O interfaces

contributor authorJaeha Kim
date accessioned2020-03-12T21:31:42Z
date available2020-03-12T21:31:42Z
date issued2014
identifier other6946077.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051709?show=full
formatgeneral
languageEnglish
publisherIEEE
titleAdvanced modeling and simulation of state-of-the-art high-speed I/O interfaces
typeConference Paper
contenttypeMetadata Only
identifier padid8181798
subject keywordsCMOS integrated circuits
subject keywordsn equalisers
subject keywordsn injection locked oscillators
subject keywordsn low-power electronics
subject keywordsn radio transmitters
subject keywordsn CMOS
subject keywordsn analog control
subject keywordsn automatic phase calibration
subject keywordsn bit rate 8 Gbit/s to 16 Gbit/s
subject keywordsn capacitively driven low-swing global clock distribution
subject keywordsn channel losses
subject keywordsn dynamic power scaling
subject keywordsn energy efficiency
subject keywordsn equalizer taps
subject keywordsn impedance-modulated 2-tap equalizer
subject keywordsn injection-locked oscillators
subject keywordsn local ILO-generated quarter-rate clocks
identifier doi10.1109/ISSCC.2014.6757507
journal titleustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
filesize9535796
citations0


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