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Cache Simulation for Instruction Set Simulator QEMU

contributor authorTran Van Dung
contributor authorTaniguchi, I.
contributor authorTomiyama, H.
date accessioned2020-03-12T21:30:09Z
date available2020-03-12T21:30:09Z
date issued2014
identifier other6945730.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051572?show=full
formatgeneral
languageEnglish
publisherIEEE
titleCache Simulation for Instruction Set Simulator QEMU
typeConference Paper
contenttypeMetadata Only
identifier padid8181631
subject keywordsCMOS digital integrated circuits
subject keywordsn circuit tuning
subject keywordsn clock and data recovery circuits
subject keywordsn interference suppression
subject keywordsn jitter
subject keywordsn oscillators
subject keywordsn phase detectors
subject keywordsn phase locked loops
subject keywordsn BBPD
subject keywordsn CMOS technology
subject keywordsn DCO
subject keywordsn LC oscillators
subject keywordsn automatic frequency acquisition
subject keywordsn bang-bang phase detector
subject keywordsn bit rate 4 Gbit/s to 10.5 Gbit/s
subject keywordsn clock and data recovery circuit
subject keywordsn continuous-rate digital CDR
subject keywordsn digitally controlled oscillator
subject keywordsn frequency detectors
subject keywordsn jit
identifier doi10.1109/ISSCC.2014.6757377
journal titleependable, Autonomic and Secure Computing (DASC), 2014 IEEE 12th International Conference on
filesize1448313
citations0


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