Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm
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سال
: 2014شناسه الکترونیک: 10.1109/DFT.2014.6962093
کلیدواژه(گان): MRAM devices,reliability,CMOS integration capability,STT-MRAM,aging phenomena,block level granularity,error correction,magnetic random access memory,process variability,reliability estimation,spin transfer torque MRAM,Discrete Fourier transforms,Error correction codes,Fault tolerance,Fault tolerant systems,Nanotechnology,Very large scale integration,Emerging memories,Memory Reliability,STT-MRAM
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Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm
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| contributor author | Leyva, P. | |
| contributor author | Domenech-Asensi, G. | |
| contributor author | Garrigos, J. | |
| contributor author | Illade-Quinteiro, J. | |
| contributor author | Brea, V.M. | |
| contributor author | Lopez, P. | |
| contributor author | Cabello, D. | |
| date accessioned | 2020-03-12T21:09:33Z | |
| date available | 2020-03-12T21:09:33Z | |
| date issued | 2014 | |
| identifier other | 6927409.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1039032 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8165774 | |
| subject keywords | MRAM devices | |
| subject keywords | reliability | |
| subject keywords | CMOS integration capability | |
| subject keywords | STT-MRAM | |
| subject keywords | aging phenomena | |
| subject keywords | block level granularity | |
| subject keywords | error correction | |
| subject keywords | magnetic random access memory | |
| subject keywords | process variability | |
| subject keywords | reliability estimation | |
| subject keywords | spin transfer torque MRAM | |
| subject keywords | Discrete Fourier transforms | |
| subject keywords | Error correction codes | |
| subject keywords | Fault tolerance | |
| subject keywords | Fault tolerant systems | |
| subject keywords | Nanotechnology | |
| subject keywords | Very large scale integration | |
| subject keywords | Emerging memories | |
| subject keywords | Memory Reliability | |
| subject keywords | STT-MRAM | |
| identifier doi | 10.1109/DFT.2014.6962093 | |
| journal title | ield Programmable Logic and Applications (FPL), 2014 24th International Conference on | |
| filesize | 419838 | |
| citations | 0 |