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Novel configurable logic block architecture exploiting controllable-polarity transistors

contributor authorGaillardon, P.-E. , Xifan Tang , De Micheli, G.
date accessioned2020-03-12T20:17:18Z
date available2020-03-12T20:17:18Z
date issued2014
identifier other6861338.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1008957?show=full
formatgeneral
languageEnglish
publisherIEEE
titleNovel configurable logic block architecture exploiting controllable-polarity transistors
typeConference Paper
contenttypeMetadata Only
identifier padid8130934
subject keywordsBayes methods
subject keywordsMarkov processes
subject keywordsMonte Carlo methods
subject keywordsdiseases
subject keywordsdocument handling
subject keywordselectronic health records
subject keywordstree data structures
subject keywordsEMRs dataset
subject keywordsHDP
subject keywordsMCMC technique
subject keywordsPolyVascular disease
subject keywordsdiagnosis codes
subject keywordsdocument corpus
subject keywordselectronic medical records
subject keywordshierarchical Bayesian models
subject keywordshierarchical Dirichlet process
subject keywordsinference method
subject keywordsreal world medical dataset
subject keywordssemantic tree structure
subject keywordssemantically-coherent disease topic discovery
subject keywordsside information
subject keywordstopic discovery regularization
subject keywordswd-dCRF
subject keywordsword-dista
identifier doi10.1109/ICPR.2014.234
journal titleeconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium
filesize280077
citations0


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