A new method for 2D-vector blood flow imaging based on unconventional beamforming techniques
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: 2014DOI: 10.1109/ICCSP.2014.6950008
Keyword(s): field programmable gate arrays,floating point arithmetic,hardware description languages,low-power electronics,microprocessor chips,pipeline processing,reduced instruction set computing,Altera Cyclone DEII FPGA,Modelsim,Quartus II 10.1 suite,RTL coding,branch instruction,clock gating,double precision floating point arithmetic,dynamic branch prediction,hardware description language Verilog HDL,instruction pipeline,low power pipelined RISC processor,word length 64 bit,Clocks,Com
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A new method for 2D-vector blood flow imaging based on unconventional beamforming techniques
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| date accessioned | 2020-03-12T20:09:45Z | |
| date available | 2020-03-12T20:09:45Z | |
| date issued | 2014 | |
| identifier other | 6854579.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1004203 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A new method for 2D-vector blood flow imaging based on unconventional beamforming techniques | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8125525 | |
| subject keywords | field programmable gate arrays | |
| subject keywords | floating point arithmetic | |
| subject keywords | hardware description languages | |
| subject keywords | low-power electronics | |
| subject keywords | microprocessor chips | |
| subject keywords | pipeline processing | |
| subject keywords | reduced instruction set computing | |
| subject keywords | Altera Cyclone DEII FPGA | |
| subject keywords | Modelsim | |
| subject keywords | Quartus II 10.1 suite | |
| subject keywords | RTL coding | |
| subject keywords | branch instruction | |
| subject keywords | clock gating | |
| subject keywords | double precision floating point arithmetic | |
| subject keywords | dynamic branch prediction | |
| subject keywords | hardware description language Verilog HDL | |
| subject keywords | instruction pipeline | |
| subject keywords | low power pipelined RISC processor | |
| subject keywords | word length 64 bit | |
| subject keywords | Clocks | |
| subject keywords | Com | |
| identifier doi | 10.1109/ICCSP.2014.6950008 | |
| journal title | coustics, Speech and Signal Processing (ICASSP), 2014 IEEE International Conference on | |
| filesize | 807529 | |
| citations | 0 | |
| contributor rawauthor | Lenge, M. , Ramalli, A. , Cellai, A. , Tortoli, P. , Cachard, C. , Liebgott, H. |