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STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies

date accessioned2020-03-12T20:08:06Z
date available2020-03-12T20:08:06Z
date issued2014
identifier other6853233.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1003187?show=full
formatgeneral
languageEnglish
publisherIEEE
titleSTAG: Spintronic-Tape Architecture for GPGPU cache hierarchies
typeConference Paper
contenttypeMetadata Only
identifier padid8124368
subject keywordscollision avoidance
subject keywordshandicapped aids
subject keywordsinfrared imaging
subject keywordsmotion control
subject keywordswheelchairs
subject keywordsautomatic motion control
subject keywordscaregivers
subject keywordscollision avoidance
subject keywordsdaily life activities
subject keywordsdisable people mobility
subject keywordsdisable society
subject keywordseye blink movements
subject keywordseye lid movement
subject keywordsindependent mobility
subject keywordsinfrared radiation
subject keywordslow intensity infrared rays
subject keywordsmechanical device
subject keywordsmotorized wheelchair
subject keywordsphysical deficiency
subject keywordsphysical inability
subject keywordspowered wheel chair
subject keywordsAcoustics
subject keywordsIntegrated optics
subject keywordsMagnetic cores
subject keywordsOptical control
subject keywordsOptical reflec
identifier doi10.1109/ICACCCT.2014.7019245
journal titleomputer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on
filesize1575151
citations0
contributor rawauthorVenkatesan, R. , Ramasubramanian, S.G. , Venkataramani, S. , Roy, K. , Raghunathan, A.


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