A 155 GHz 20 Gbit/s QPSK transceiver in 45nm CMOS
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Year
: 2014DOI: 10.1109/DCIS.2014.7035554
Keyword(s): Dynamic and Partial Reconfiguration,Evolutionary Algorithms,Evolvable Hardware,FPGA,WSN
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A 155 GHz 20 Gbit/s QPSK transceiver in 45nm CMOS
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| date accessioned | 2020-03-12T20:06:29Z | |
| date available | 2020-03-12T20:06:29Z | |
| date issued | 2014 | |
| identifier other | 6851743.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1002122 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A 155 GHz 20 Gbit/s QPSK transceiver in 45nm CMOS | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8123121 | |
| subject keywords | Dynamic and Partial Reconfiguration | |
| subject keywords | Evolutionary Algorithms | |
| subject keywords | Evolvable Hardware | |
| subject keywords | FPGA | |
| subject keywords | WSN | |
| identifier doi | 10.1109/DCIS.2014.7035554 | |
| journal title | adio Frequency Integrated Circuits Symposium, 2014 IEEE | |
| filesize | 492736 | |
| citations | 0 | |
| contributor rawauthor | Yang, Y. , Zihir, S. , Lin, H. , Inac, O. , Shin, W. , Rebeiz, G.M. |