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Considering variation and aging in a full chip design methodology at system level

date accessioned2020-03-12T20:05:05Z
date available2020-03-12T20:05:05Z
date issued2014
identifier other6850386.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1001183?show=full
formatgeneral
languageEnglish
publisherIEEE
titleConsidering variation and aging in a full chip design methodology at system level
typeConference Paper
contenttypeMetadata Only
identifier padid8122046
subject keywordsComputer architecture
subject keywordsComputers
subject keywordsData transfer
subject keywordsField programmable gate arrays
subject keywordsRadar imaging
subject keywordsFMCW
subject keywordsFPGA
subject keywordsRadar
subject keywordsSuperSpeed
subject keywordsUSB-3.0
identifier doi10.1109/ReConFig.2014.7032498
journal titlelectronic System Level Synthesis Conference (ESLsyn), Proceedings of the 2014
filesize237888
citations0
contributor rawauthorHelms, D. , Gruttner, K. , Eilers, R. , Metzdorf, M. , Hylla, K. , Poppen, F. , Nebel, W.


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