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[IEEE 2008 IEEE International SOC Conference (SOCC) - Newport Beach, CA, USA (2008.09.17-2008.09.20)] 2008 IEEE International SOC Conference - A low power 32 nanometer CMOS digitally controlled oscillator

Type: Journal Paper

Author : Jun Zhao,; Yong-bin Kim,

Year: 2008

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A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

Type: Journal Paper

Author : Yongsuk Choi; Yong-Bin Kim

Year: 2015

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Circuit implementation of FitzHugh-Nagumo neuron model using Field Programmable Analog Arrays

Type: Journal Paper

Author : Jun Zhao; Yong-Bin Kim

Year: 2007

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Fault Tolerant Source Routing for Network-on-chip

Type: Conference Paper

Author : Young Bok Kim; Yong-Bin Kim

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A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

Type: Conference Paper

Author : In-Seok Jung; Yong-Bin Kim

Publisher: IEEE

Year: 2014

A high speed low power modulo 2ⁿ+1 multiplier design using carbon-nanotube technology

Type: Journal Paper

Author : He Qi; Yong-Bin Kim; Minsu Choi

Year: 2012

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A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method

Type: Journal Paper

Author : Yongsuk Choi; Heungjun Jeon; Yong-Bin Kim

Year: 2013

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Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

Type: Journal Paper

Author : Haiyang Zhu; Ron Kapusta; Yong-Bin Kim

Year: 2015

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

Type: Journal Paper

Author : Yongsuk Choi; Yong-Bin Kim; In-Seok Jung

Year: 2016

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A 10-bit 64MS/s SAR ADC using variable clock period method

Type: Conference Paper

Author : In-Seok Jung; Marvin Onabajo; Yong-Bin Kim

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[IEEE 2008 IEEE International SOC Conference (SOCC) - Newport Beach, CA, USA (2008.09.17-2008.09.20)] 2008 IEEE International SOC Conference - A low power 32 nanometer CMOS digitally controlled oscillator

A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

Circuit implementation of FitzHugh-Nagumo neuron model using Field Programmable Analog Arrays

Fault Tolerant Source Routing for Network-on-chip

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

A high speed low power modulo 2ⁿ+1 multiplier design using carbon-nanotube technology

A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

A 10-bit 64MS/s SAR ADC using variable clock period method

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[IEEE 2008 IEEE International SOC Conference (SOCC) - Newport Beach, CA, USA (2008.09.17-2008.09.20)] 2008 IEEE International SOC Conference - A low power 32 nanometer CMOS digitally controlled oscillator

A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer

Circuit implementation of FitzHugh-Nagumo neuron model using Field Programmable Analog Arrays

Fault Tolerant Source Routing for Network-on-chip

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

A high speed low power modulo 2n+1 multiplier design using carbon-nanotube technology

A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method

Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier

A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration

A 10-bit 64MS/s SAR ADC using variable clock period method

A high speed low power modulo 2ⁿ+1 multiplier design using carbon-nanotube technology