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Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

Type: Journal Paper

Author : Wenbo Wan; Haijun Lou; Ying Xiao; Xinnan Lin

Year: 2018

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A Compact Model for Double-Gate Heterojunction Tunnel FETs

Type: Journal Paper

Author : Yunpeng Dong; Lining Zhang; Xiangbin Li; Xinnan Lin; Mansun Chan

Year: 2016

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Analytical model of the subthreshold behavior in short-channel junctionless cylindrical surrounding-gate mosfets

Type: Conference Paper

Author : Baili Zhang; Haijun Lou; Dan Li; Xinnan Lin; Mansun Chan

Publisher: IEEE

Year: 2014

A superjunction insulated Gate Bipolar Transistor with bilateral HK insulators: A solution to charge imbalance

Type: Conference Paper

Author : Hang Wei; Jiang, Frank X.C.; Xinnan Lin

Publisher: IEEE

Year: 2014

A low loss SOI lateral trench IGBT and superjunction device with insulated trench barrier

Type: Conference Paper

Author : Hang Meng; Jian Chen; Jiang, F.X.C.; Xinnan Lin

Publisher: IEEE

Year: 2014

A superjunction snapback-free reverse-conducting insulated gate bipolar transistor with anti-parallel p-i-n diode

Type: Conference Paper

Author : Ji Yu; Jiang, F.X.C.; Hang Wei; Xinnan Lin

Publisher: IEEE

Year: 2014

Dual trench gates SOI LIGBT with low conduction loss

Type: Conference Paper

Author : Meihua Liu; Jiang, F.X.C.; Xinnan Lin

Publisher: IEEE

Year: 2014

Double-gate tunneling FET with asymmetric gate structure and pocket source

Type: Journal Paper

Author : Dan Li; Haijun Lou; Xinnan Lin; Lining Zhang; Mansun Chan

Year: 2014

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A Junctionless Nanowire Transistor With a Dual-Material Gate

Type: Journal Paper

Author : Haijun Lou; Lining Zhang; Yunxi Zhu; Xinnan Lin; Shengqi Yang; Jin He; Mansun Chan

Year: 2012

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Analytical Drain Current Model for Amorphous InGaZnO Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

Type: Journal Paper

Author : Hongyu He; Yuan Liu; Binghui Yan; Xinnan Lin; Xueren Zheng; Shengdong Zhang

Year: 2017

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Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

A Compact Model for Double-Gate Heterojunction Tunnel FETs

Analytical model of the subthreshold behavior in short-channel junctionless cylindrical surrounding-gate mosfets

A superjunction insulated Gate Bipolar Transistor with bilateral HK insulators: A solution to charge imbalance

A low loss SOI lateral trench IGBT and superjunction device with insulated trench barrier

A superjunction snapback-free reverse-conducting insulated gate bipolar transistor with anti-parallel p-i-n diode

Dual trench gates SOI LIGBT with low conduction loss

Double-gate tunneling FET with asymmetric gate structure and pocket source

A Junctionless Nanowire Transistor With a Dual-Material Gate

Analytical Drain Current Model for Amorphous InGaZnO Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States

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Source/Drain Engineered Charge-Plasma Junctionless Transistor for the Immune of Line Edge Roughness Effect

A Compact Model for Double-Gate Heterojunction Tunnel FETs

Analytical model of the subthreshold behavior in short-channel junctionless cylindrical surrounding-gate mosfets

A superjunction insulated Gate Bipolar Transistor with bilateral HK insulators: A solution to charge imbalance

A low loss SOI lateral trench IGBT and superjunction device with insulated trench barrier

A superjunction snapback-free reverse-conducting insulated gate bipolar transistor with anti-parallel p-i-n diode

Dual trench gates SOI LIGBT with low conduction loss

Double-gate tunneling FET with asymmetric gate structure and pocket source

A Junctionless Nanowire Transistor With a Dual-Material Gate

Analytical Drain Current Model for Amorphous InGaZnO Thin-Film Transistors at Different Temperatures Considering Both Deep and Tail Trap States