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Author : Yu-Sheng Chen; Heng-Yuan Lee; Pang-Shiu Chen; Wei-Su Chen; Kan-Hsueh Tsai; Pei-Yi Gu; Tai-Yuan Wu; Chen-Han Tsai; Rahaman, S.Z.; Yu-De Lin; Chen, Fan; Ming-Jinn Tsai; Tzu-Kun Ku

Publisher: IEEE

Year: 2014

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Type: Journal Paper

Author : Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Chen, F.T.; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yue-Der Chih

Publisher: IEEE

Year: 2014

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics

Type: Journal Paper

Author : Meng-Fan Chang; Albert Lee; Chien-Chen Lin; Mon-Shu Ho; Ping-Cheng Chen; Chia-Chen Kuo; Ming-Pin Chen; Pei-Ling Tseng; Tzu-Kun Ku; Chien-Fu Chen; Kai-Shin Li; Jia-Min Shieh

Year: 2015

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Scaling Properties of Step-Etch Perpendicular Magnetic Tunnel Junction With Dual-CoFeB/MgO Interfaces

Type: Journal Paper

Author : Cheng-Wei Chien; Ding-Yeong Wang; Sheng-Huang Huang; Kuei-Hung Shen; Shan-Yi Yang; Jia-Hong Shyu; Chiung-Yu Lo; Keng-Ming Kuo; Young-Shying Chen; Yung-Hung Wang; Tzu-Kun Ku; Duan-Li Deng

Publisher: IEEE

Year: 2014

A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application

Type: Journal Paper

Author : Shyh-Shyuan Sheu; Chia-Chen Kuo; Meng-Fan Chang; Pei-Ling Tseng; Lin Chih-Sheng; Min-Chuan Wang; Chih-He Lin; Wen-Pin Lin; Tsai-Kan Chien; Sih-Han Lee; Szu-Chieh Liu; Heng-Yuan Lee; Pang-Shiu Chen; Yu-Sheng Chen; Ching-Chih Hsu; Frederick T. Chen; Keng-Li Su; Tzu-Kun Ku; Ming-Jinn Tsai; Ming-Jer Kao

Year: 2013

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Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Challenges at circuit designs for resistive-type Nonvolatile memory and nonvolatile logics in mobile and cloud applications

Novel Defects-Trapping <formula formulatype="inline"> <img src="/images/tex/21375.gif" alt="{\\rm TaO}_{\\rm X}/{\\rm HfO}_{\\rm X}"> </formula> RRAM With Reliable Self-Compliance, High Nonlinearity, and Ultra-Low Current

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics

Scaling Properties of Step-Etch Perpendicular Magnetic Tunnel Junction With Dual-CoFeB/MgO Interfaces

A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application

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Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Challenges at circuit designs for resistive-type Nonvolatile memory and nonvolatile logics in mobile and cloud applications

Novel Defects-Trapping <formula formulatype="inline"> <img src="/images/tex/21375.gif" alt="{\\rm TaO}_{\\rm X}/{\\rm HfO}_{\\rm X}"> </formula> RRAM With Reliable Self-Compliance, High Nonlinearity, and Ultra-Low Current

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics

Scaling Properties of Step-Etch Perpendicular Magnetic Tunnel Junction With Dual-CoFeB/MgO Interfaces

A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application