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Energy-Delay Optimization of the STT MRAM Write Operation Under Process Variations

Type: Journal Paper

Author : Dongsoo Lee; Roy, Kaushik

Publisher: IEEE

Year: 2014

Individuality of Isolated Bangla Characters

Type: Conference Paper

Author : Halder, Chayan; Roy, Kaushik

Publisher: IEEE

Year: 2014

A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology

Type: Journal Paper

Author : Soo Youn Kim; Roy, Kaushik

Publisher: IEEE

Year: 2014

An Enhanced Voltage Programming Pixel Circuit for Compensating GB-Induced Variations in Poly-Si TFTs for AMOLED Displays

Type: Journal Paper

Author : Chih-Hsiang Ho; Chao Lu; Roy, Kaushik

Publisher: IEEE

Year: 2014

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Type: Journal Paper

Author : Sharma, Ashok; Goud, Akkala Arun; Roy, Kaushik

Publisher: IEEE

Year: 2014

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

Type: Journal Paper

Author : Deliang Fan; Sharad, Mrigank; Roy, Kaushik

Publisher: IEEE

Year: 2014

[ACM Press the 49th Annual Design Automation Conference - San Francisco, California (2012.06.03-2012.06.07)] Proceedings of the 49th Annual Design Automation Conference on - DAC \'12 - Cognitive computing with spin-based neural networks

Type: Journal Paper

Author : Sharad, Mrigank; Augustine, Charles; Panagopoulos, Georgios; Roy, Kaushik

Year: 2012

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Large amplitude double-layers in a dusty plasma with a q-nonextensive electron velocity distribution and two-temperature isothermal ions

Type: Journal Paper

Author : Roy, Kaushik; Saha, Taraknath; Chatterjee, Prasanta; Tribeche, Mouloud

Year: 2012

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Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

Type: Journal Paper

Author : Xuanyao Fong; Yusung Kim; Choday, Sri Harsha; Roy, Kaushik

Publisher: IEEE

Year: 2014

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Type: Journal Paper

Author : Kon-Woo Kwon; Choday, Sri Harsha; Yusung Kim; Roy, Kaushik

Publisher: IEEE

Year: 2014

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Energy-Delay Optimization of the STT MRAM Write Operation Under Process Variations

Individuality of Isolated Bangla Characters

A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology

An Enhanced Voltage Programming Pixel Circuit for Compensating GB-Induced Variations in Poly-Si TFTs for AMOLED Displays

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

[ACM Press the 49th Annual Design Automation Conference - San Francisco, California (2012.06.03-2012.06.07)] Proceedings of the 49th Annual Design Automation Conference on - DAC \'12 - Cognitive computing with spin-based neural networks

Large amplitude double-layers in a dusty plasma with a q-nonextensive electron velocity distribution and two-temperature isothermal ions

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

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Energy-Delay Optimization of the STT MRAM Write Operation Under Process Variations

Individuality of Isolated Bangla Characters

A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology

An Enhanced Voltage Programming Pixel Circuit for Compensating GB-Induced Variations in Poly-Si TFTs for AMOLED Displays

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

[ACM Press the 49th Annual Design Automation Conference - San Francisco, California (2012.06.03-2012.06.07)] Proceedings of the 49th Annual Design Automation Conference on - DAC \'12 - Cognitive computing with spin-based neural networks

Large amplitude double-layers in a dusty plasma with a q-nonextensive electron velocity distribution and two-temperature isothermal ions

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture