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Now showing items 1-10 of 12

Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency

Type: Journal Paper

Author : Paulo C. Santos; Marco A. Z. Alves; Matthias Diener; Luigi Carro; Philippe O. A. Navaux

Year: 2016

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Process Mapping Based on Memory Access Traces

Type: Journal Paper

Author : Eduardo H.M. Cruz; Marco A.Z. Alves; Philippe O.A. Navaux

Year: 2010

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Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

Type: Journal Paper

Author : Henrique C. Freitas; Dalton M. Colombo; Fernanda L. Kastensmidt; Philippe O. A. Navaux

Year: 2007

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Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols

Type: Journal Paper

Author : Eduardo H.M. Cruz; Matthias Diener; Marco A.Z. Alves; Philippe O.A. Navaux

Year: 2014

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Characterizing communication and page usage of parallel applications for thread and data mapping

Type: Journal Paper

Author : Matthias Diener; Eduardo H.M. Cruz; Laércio L. Pilla; Fabrice Dupros; Philippe O.A. Navaux

Year: 2015

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Communication-aware process and thread mapping using online communication detection

Type: Journal Paper

Author : Matthias Diener; Eduardo H.M. Cruz; Philippe O.A. Navaux; Anselm Busse; Hans-Ulrich Heiß

Year: 2015

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Evaluating High Performance Computing on the Windows Azure Platform

Type: Journal Paper

Author : Eduardo Roloff; Francis Birck; Matthias Diener; Alexandre Carissimi; Philippe O.A. Navaux

Year: 2012

Energy Savings via Dead Sub-Block Prediction

Type: Journal Paper

Author : Marco A.Z. Alves; Khubaib; Eiman Ebrahimi; Veynu T. Narasiman; Carlos Villavieja; Philippe O.A. Navaux; Yale N. Patt

Year: 2012

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Evaluating application performance and energy consumption on hybrid CPU+GPU architecture

Type: Journal Paper

Author : Edson Luiz Padoin; Laércio Lima Pilla; Francieli Zanon Boito; Rodrigo Virote Kassick; Pedro Velho; Philippe O. A. Navaux

Year: 2012

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A topology-aware load balancing algorithm for clustered hierarchical multi-core machines

Type: Journal Paper

Author : Laércio L. Pilla; Christiane P. Ribeiro; Pierre Coucheney; François Broquedis; Bruno Gaujal; Philippe O.A. Navaux; Jean-François Méhaut

Year: 2014

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Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency

Process Mapping Based on Memory Access Traces

Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols

Characterizing communication and page usage of parallel applications for thread and data mapping

Communication-aware process and thread mapping using online communication detection

Evaluating High Performance Computing on the Windows Azure Platform

Energy Savings via Dead Sub-Block Prediction

Evaluating application performance and energy consumption on hybrid CPU+GPU architecture

A topology-aware load balancing algorithm for clustered hierarchical multi-core machines

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Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency

Process Mapping Based on Memory Access Traces

Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs

Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols

Characterizing communication and page usage of parallel applications for thread and data mapping

Communication-aware process and thread mapping using online communication detection

Evaluating High Performance Computing on the Windows Azure Platform

Energy Savings via Dead Sub-Block Prediction

Evaluating application performance and energy consumption on hybrid CPU+GPU architecture

A topology-aware load balancing algorithm for clustered hierarchical multi-core machines