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Now showing items 1-6 of 6

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Type: Journal Paper

Author : Condo, Carlo; Baghdadi, Amer; Masera, Guido

Publisher: IET

Year: 2014

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

Type: Journal Paper

Author : Martina, Maurizio; Papaharalabos, Stylianos; Mathiopoulos, P. Takis; Masera, Guido

Publisher: IEEE

Year: 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

Type: Journal Paper

Author : Guoping Xiao; Martina, Maurizio; Masera, Guido; Piccinini, G.

Publisher: IEEE

Year: 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

Type: Journal Paper

Author : Martina, Maurizio; Condo, Carlo; Masera, Guido; Zamboni, Maurizio

Publisher: IEEE

Year: 2014

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Type: Journal Paper

Author : Awais, Muhammad; Masera, Guido; Martina, Maurizio; Montorsi, Guido

Publisher: IEEE

Year: 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

Type: Journal Paper

Author : Condo, Carlo; Martina, Maurizio; Piccinini, G.; Masera, Guido

Publisher: IEEE

Year: 2014

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Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

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Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced