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Now showing items 1-10 of 11

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

Type: Journal Paper

Author : Junwhan Ahn; Kiyoung Choi

Publisher: IEEE

Year: 2014

An FPGA implementation of high-throughput key-value store using Bloom filter

Type: Conference Paper

Author : Jae Min Cho , Kiyoung Choi

Publisher: IEEE

Year: 2014

AIM

Type: Journal Paper

Author : Junwhan Ahn; Sungjoo Yoo; Kiyoung Choi

Year: 2016

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Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture

Type: Journal Paper

Author : Kyuseung Han; Ganghee Lee; Kiyoung Choi

Year: 2014

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Leveraging parallelism in the presence of control flow on CGRAs

Type: Conference Paper

Author : Jihyun Ryoo , Kyuseung Han , Kiyoung Choi

Publisher: IEEE

Year: 2014

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Type: Conference Paper

Author : Junwhan Ahn , Sungjoo Yoo , Kiyoung Choi

Publisher: IEEE

Year: 2014

Concept-aware ensemble system for pedestrian detection

Type: Conference Paper

Author : Helin Lin , Kyounghoon Kim , Kiyoung Choi

Publisher: IEEE

Year: 2014

Dynamic power management of off-chip links for Hybrid Memory Cubes

Type: Conference Paper

Author : Junwhan Ahn , Sungjoo Yoo , Kiyoung Choi

Publisher: IEEE

Year: 2014

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Type: Journal Paper

Author : Byungil Jeong; Sungjoo Yoo; Sunghyun Lee; Kiyoung Choi

Year: 2000

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Deep neural networks with weighted spikes

Type: Journal Paper

Author : Jaehyun Kim; Heesu Kim; Subin Huh; Jinho Lee; Kiyoung Choi

Year: 2018

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LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

An FPGA implementation of high-throughput key-value store using Bloom filter

AIM

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture

Leveraging parallelism in the presence of control flow on CGRAs

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Concept-aware ensemble system for pedestrian detection

Dynamic power management of off-chip links for Hybrid Memory Cubes

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Deep neural networks with weighted spikes

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LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

An FPGA implementation of high-throughput key-value store using Bloom filter

AIM

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture

Leveraging parallelism in the presence of control flow on CGRAs

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Concept-aware ensemble system for pedestrian detection

Dynamic power management of off-chip links for Hybrid Memory Cubes

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Deep neural networks with weighted spikes