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نمایش تعداد 1-10 از 27

Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS

نوع: Journal Paper

نویسنده : Kyongsu Lee; Jae-Yoon Sim

ناشر: IEEE

سال: 2014

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs

نوع: Journal Paper

نویسنده : Jae-Yoon Sim; Kee-Won Kwon; Ki-Chul Chun

سال: 2004

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A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS

نوع: Journal Paper

نویسنده : Young-Hun Seo; Seon-Kyoo Lee; Jae-Yoon Sim

سال: 2011

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Untitled

نوع: Journal Paper

نویسنده : Ji-Yong Um; Jae-Yoon Sim; Hong-June Park

سال: 2010

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An Approximate Closed-Form Channel Model for Diverse Interconnect Applications

نوع: Journal Paper

نویسنده : Minsoo Choi; Jae-Yoon Sim; Hong-June Park; Byungsub Kim

ناشر: IEEE

سال: 2014

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface

نوع: Journal Paper

نویسنده : Kihwan Seong; Won-Cheol Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park

سال: 2017

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A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio

نوع: Conference Paper

نویسنده : Hye-Jung Kwon; Jae-seung Lee; Jae-Yoon Sim; Hong-June Park

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A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS

نوع: Journal Paper

نویسنده : Young-Hun Seo; Jun-Seok Kim; Hong-June Park; Jae-Yoon Sim

ناشر: IEEE

سال: 2012

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Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

نوع: Journal Paper

نویسنده : Hye-Jung Kwon; Jae-Seung Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park

سال: 2014

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2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology

نوع: Journal Paper

نویسنده : Seungho Han; Sooeun Lee; Minsoo Choi; Jae-Yoon Sim; Hong-June Park; Byungsub Kim

سال: 2014

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Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS

Untitled

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface

A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology

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Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS

Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18- CMOS

Untitled

An Approximate Closed-Form Channel Model for Diverse Interconnect Applications

All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface

A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology