Search

Now showing items 1-10 of 13

Vortex-based spin transfer oscillator compact model for IC design

Type: Journal Paper

Author : Nicolas Locatelli; Damir Vodenicarevic; Weisheng Zhao; Jacques-Olivier Klein; Julie Grollier; Damien Querlioz

Year: 2015

Request PDF

Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Type: Conference Paper

Author : Yue Zhang; WeiSheng Zhao; Jacques-Olivier Klein; Wang Kang; Damien Querlioz; Claude Chappert; Dafine Ravelosona

Request PDF

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

Type: Journal Paper

Author : Djaafar Chabi; Weisheng Zhao; Erya Deng; Yue Zhang; Nesrine Ben Romdhane; Jacques-Olivier Klein; Claude Chappert

Year: 2014

Request PDF

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Type: Journal Paper

Author : Wang Kang; Liuyang Zhang; Weisheng Zhao; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Claude Chappert

Year: 2015

Request PDF

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Type: Journal Paper

Author : Wang Kang; Liuyang Zhang; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Weisheng Zhao

Year: 2015

Request PDF

Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits

Type: Journal Paper

Author : Erya Deng; Wang Kang; Yue Zhang; Jacques-Olivier Klein; Claude Chappert; Weisheng Zhao

Year: 2015

Request PDF

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

Type: Journal Paper

Author : Liuyang Zhang; Wang Kang; Youguang Zhang; Yuanqing Cheng; Lang Zeng; Jacques-Olivier Klein; Weisheng Zhao

Year: 2015

Request PDF

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Type: Journal Paper

Author : Yue Zhang; Chao Zhang; Jiang Nan; Zhizhong Zhang; Xueying Zhang; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun; Weisheng Zhao

Year: 2016

Request PDF

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Type: Journal Paper

Author : Yue Zhang; Weisheng Zhao; Guillaume Prenat; Thibaut Devolder; Jacques-Olivier Klein; Claude Chappert; Bernard Dieny; Dafine Ravelosona

Year: 2013

Request PDF

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes

Type: Journal Paper

Author : Yue Zhang; Bonan Yan; Wang Kang; Yuanqing Cheng; Jacques-Olivier Klein; Youguang Zhang; Yiran Chen; Weisheng Zhao

Year: 2015

Request PDF

Search

Vortex-based spin transfer oscillator compact model for IC design

Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes

Author

Year

Type

Language (ISO)

Content Type

Publication Title

Search

Filters

Vortex-based spin transfer oscillator compact model for IC design

Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes