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Now showing items 1-7 of 7

Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Type: Conference Paper

Author : Yue Zhang; WeiSheng Zhao; Jacques-Olivier Klein; Wang Kang; Damien Querlioz; Claude Chappert; Dafine Ravelosona

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Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Type: Journal Paper

Author : Wang Kang; Liuyang Zhang; Weisheng Zhao; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Claude Chappert

Year: 2015

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Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Type: Journal Paper

Author : Wang Kang; Liuyang Zhang; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Weisheng Zhao

Year: 2015

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A Multi-Level Cell for STT-MRAM Realized by Capping Layer Adjustment

Type: Journal Paper

Author : Mengxing Wang; Shouzhong Peng; Yue Zhang; Yu Zhang; Youguang Zhang; Qianfan Zhang; Dafine Ravelosona; Weisheng Zhao

Year: 2015

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Complementary Spintronic Logic with Spin Hall Effect Driven Magnetic Tunnel Junction

Type: Journal Paper

Author : Wang Kang; Chentian Zheng; Youguang Zhang; Dafine Ravelosona; Weifeng Lv; Weisheng ZHAO

Year: 2015

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Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Type: Journal Paper

Author : Yue Zhang; Chao Zhang; Jiang Nan; Zhizhong Zhang; Xueying Zhang; Jacques-Olivier Klein; Dafine Ravelosona; Guangyu Sun; Weisheng Zhao

Year: 2016

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Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

Type: Journal Paper

Author : Yue Zhang; Weisheng Zhao; Guillaume Prenat; Thibaut Devolder; Jacques-Olivier Klein; Claude Chappert; Bernard Dieny; Dafine Ravelosona

Year: 2013

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Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

A Multi-Level Cell for STT-MRAM Realized by Capping Layer Adjustment

Complementary Spintronic Logic with Spin Hall Effect Driven Magnetic Tunnel Junction

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications

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Multi-level cell Spin Transfer Torque MRAM based on stochastic switching

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM

Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

A Multi-Level Cell for STT-MRAM Realized by Capping Layer Adjustment

Complementary Spintronic Logic with Spin Hall Effect Driven Magnetic Tunnel Junction

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System

Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications