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RISArea and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Year: 2010
Abstract:
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particularly when high-order gain calibration is ...
Digital Background Calibration of Capacitor Mismatch Errors in Pipelined ADCs
Year: 2006
Abstract:
A digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the feedback capacitor...
A Reconfigurable and Power-Scalable 10-12 bit 0.4-44 MS/s Pipelined ADC with 0.35-0.5 pJ/step in 1.2 V 90 nm Digital CMOS
Year: 2013
Abstract:
A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V ...
Traffic Monitoring Using Video Analytics in Clouds
Publisher: IEEE
Year: 2014
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
Publisher: IEEE
Year: 2014
IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration
Publisher: IEEE
Year: 2014
A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy
Publisher: IEEE
Year: 2014
Experimental assessment of gait with rhythmic auditory perturbations
Publisher: IEEE
Year: 2014
Research the relations between the traditional cultural attributes of shopping street and consumer behavior
Publisher: IEEE
Year: 2014