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Partitioning of ECE schemes components based on modified graph coloring algorithm

Type: Conference Paper

Author : Kureichik, V.V.; Kureichik, Vl.Vl.; Zaruba, D.V.

Publisher: IEEE

Year: 2014

Usage of low-temperature co-fired ceramic in hermetic packaging

Type: Conference Paper

Publisher: IEEE

Year: 2014

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Type: Journal Paper

Author : Vatankhahghadim, Aynaz; Huda, S.; Sheikholeslami, Ali

Publisher: IEEE

Year: 2014

Optimising the location and power of wireless base stations within a dynamic indoor environment

Type: Conference Paper

Author : Minkara, Rania; Shepherd, Peter

Publisher: IEEE

Year: 2014

Mixed criticality scheduling in fault-tolerant distributed real-time systems

Type: Conference Paper

Author : Thekkilakattil, Abhilash; Dobrin, Radu; Punnekkat, Sasikumar

Publisher: IEEE

Year: 2014

Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Type: Journal Paper

Author : Verma, Shalini; Kaundal, Shalu; Kaushik, B.K.

Publisher: IEEE

Year: 2014

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Partitioning of ECE schemes components based on modified graph coloring algorithm

Usage of low-temperature co-fired ceramic in hermetic packaging

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Optimising the location and power of wireless base stations within a dynamic indoor environment

Mixed criticality scheduling in fault-tolerant distributed real-time systems

Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

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Partitioning of ECE schemes components based on modified graph coloring algorithm

Usage of low-temperature co-fired ceramic in hermetic packaging

A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions

Optimising the location and power of wireless base stations within a dynamic indoor environment

Mixed criticality scheduling in fault-tolerant distributed real-time systems

Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device