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    Design of a Low-Power CMOS Comparator Circuit in Sub-Threshold Region 

    Type: Conference Paper
    Author : Aghaei jeshvaghani, Mohamad; Dolatshahi, Mehdi; Raeisi Nafchi, Shirin
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    A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations 

    Type: Conference Paper
    Author : سیده ساره مجیدی ایوری; محمد میمندی نژاد; Seyedeh Sareh Majidi Ivari; Mohammad Maymandi Nejad
    Year: 2013
    Abstract:

    Abstract— Designing logic circuits in the subthreshold regime is

    one of the most effective ways to reduce the power consumption

    of digital circuits. In the subthreshold region, the current is an

    exponential ...

    A low-power wide-range voltage level shifter using a modified Wilson current mirror 

    Type: Conference Paper
    Author : آلاء طالب زاده شوشتری; مهدی صابری; Ala Talebzadeh Shooshtari; Mehdi Saberi
    Year: 2016
    Abstract:

    In this paper, a low-power voltage level shifter is proposed which is able to convert sub-threshold voltage levels of input signal to above-threshold voltage levels. The proposed circuit is based on a modified Wilson current mirror structure which...

    A Low-Power Level-Shifting Architecture for Sub-threshold Logic Circuits 

    Type: Journal Paper
    Author : سیدرسول حسینی بلداجی; مهدی صابری; رضا لطفی; Seyed Rasool Hosseini; Mehdi Saberi; Reza Lotfi
    Year: 2016
    Abstract:

    This paper presents a power-efficient voltage level shifter converting low levels of input voltages (sub-threshold) to high levels of the output voltages (above threshold). In order to reduce the existing contention in the output nodes between pull...

    An Energy-Efficient Level Shifter for Low-Power Applications 

    Type: Conference Paper
    Author : سیدرسول حسینی بلداجی; مهدی صابری; رضا لطفی; Seyed Rasool Hosseini; Mehdi Saberi; Reza Lotfi
    Year: 2015
    Abstract:

    One effective way to reduce the power consumption of biomedical implantable devices is to employ different supply voltages for different parts of the system depending on the processing speed of each part. This, however, ...

    Design and Optimization of a P+N+IN+ Tunnel FET with Si Channel and SiGe Source 

    Type: Journal Paper
    Author : M. Kamali Moghadam; سید ابراهیم حسینی; Seyed Ebrahim Hosseini
    Year: 2012
    Abstract:

    are obtained. Moreover, the ource/channel hetero-junction is assumed graded. The grading distance is varied from zero (abrupt hetero-junction) to total channel length to achieve the best performance, i.e. low off state current, high Ion/Ioff and low sub-threshold...

    QoE-enabled transport optimisation scheme for real-time SVC video delivery 

    Type: Conference Paper
    Author : Alreshoodi, M.; Woods, J.; Musa, I.K.
    Publisher: IEEE
    Year: 2014

    Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain 

    Type: Journal Paper
    Author : Corsonello, Pasquale; Frustaci, Fabio; Lanuzza, Marco; Perri, Stefania
    Publisher: IEEE
    Year: 2014

    User-centric service environment for context aware service mash-up 

    Type: Conference Paper
    Publisher: IEEE
    Year: 2014

    A model of E-Loyalty and word-of-mouth based on e-trust in E-banking services (case study: Mellat Bank) 

    Type: Conference Paper
    Publisher: IEEE
    Year: 2014
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