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نمایش تعداد 1-10 از 61

Temperature Sensing RRAM Architecture for 3-D ICs

نوع: Journal Paper

نویسنده : Merkel, Cory E.; Kudithipudi, Dhireesha

ناشر: IEEE

سال: 2014

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

نوع: Journal Paper

نویسنده : Yi Wang; Zili Shao; Chan, Henry; Bathen, L.A.D.; Dutt, N.D.

ناشر: IEEE

سال: 2014

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

نوع: Journal Paper

نویسنده : Chi-Hsuan Cheng; Tai-Yu Cheng; Cheng-Han Du; Yi-Chang Lu; Yih-Peng Chiou; Liu, Siyuan; Tzong-Lin Wu

ناشر: IEEE

سال: 2014

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

نوع: Journal Paper

نویسنده : Halder, Sebastian; Miller, Alice; Van Puymbroeck, Jan; Nieuborg, Nancy; Beyne, Eric

ناشر: IEEE

سال: 2014

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

نوع: Conference Paper

نویسنده : Revathi, P.

ناشر: IEEE

سال: 2014

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

نوع: Journal Paper

نویسنده : Gaynor, Brad D.; Hassoun, Soha

ناشر: IEEE

سال: 2014

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

نوع: Journal Paper

نویسنده : Sangwook Han; Wentzloff, David D.

ناشر: IEEE

سال: 2014

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

نوع: Journal Paper

نویسنده : Rab, Muhammad Tauseef; Bawa, Asad Amin; Touba, Nur /A/.

ناشر: IEEE

سال: 2014

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

نوع: Journal Paper

نویسنده : Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; Li, James Chien-Mo; Chakrabarty, Krishnendu

ناشر: IEEE

سال: 2014

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

نوع: Journal Paper

نویسنده : Jolondz, Alexei; Weiss, Steven; Golander, A.

ناشر: IEEE

سال: 2014

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Temperature Sensing RRAM Architecture for 3-D ICs

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

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Temperature Sensing RRAM Architecture for 3-D ICs

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

L1&#x2013;L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters